1. Field of the Invention
The present invention relates to a structure for contact wires in a semiconductor device and, more particularly, to a method for forming a structure of wires for a semiconductor device in which pads are formed for contact in cell regions as well as core regions and periphery regions when an aspect ratio of corresponding contact holes is very high, so as to obtain stable contact wiring.
2. Discussion of the Related Art
A conventional method for forming wires of a semiconductor device will be discussed with reference to the accompanying drawings.
FIGS. 1A to 1E are cross-sectional views showing process steps of a conventional method for forming wires of a semiconductor device. First, pads are formed only in a cell region which is shown at the left hand side of the figures, but not in a core region or a periphery region which is shown at the right hand side of the figures. Pads for the core region or periphery region are formed later; see FIG. 1E.
Referring initially to FIG. 1A, an active region and a field insulating layer are formed on the entire surface of a first conductive type semiconductor substrate 1. A second conductive type well 3 is formed beneath a predetermined area of surface of the semiconductor substrate 1. A first oxide layer, a polysilicon layer, a second oxide layer are successively formed and patterned by a photo etching process with using a mask for gate electrode formation, so as to form gate oxide layers 4, gate electrodes 5, and gate cap insulating layers 6.
Lightly doped impurity ions are implanted into the substrate 1 at both sides of every gate electrode 5 to form lightly doped drain (LDD) regions 7. Next, an oxide layer is deposited on the entire surface and then etched-back to form a sidewall insulating layer 8 on both sides of every gate electrode 5. Thereafter, heavily doped impurity ions are implanted into the exposed first conductive type semiconductor substrate 1 at sides of the sidewall insulating layer 8, thus forming source/drain regions 9.
A thin third oxide layer 10 is formed on the entire surface and then an interlayer insulating layer 11 is formed for planarization by a chemical vapor deposition (CVD) process. Subsequently, a photo resist film 12 is coated on the entire surface and then partially patterned by an exposure and development process to remain over the gate electrodes 5 in the cell region which is shown at left hand of the figures.
Referring to FIG. 1B, using the photo resist pattern 12 as a mask, the interlayer insulating layer 11 and the third oxide layer 10 are anisotropically etched to expose the source/drain regions 9, thus forming contact holes.
Referring to FIG. 1C, a polysilicon layer 13 is formed on the entire surface, thus the contact holes of the cell region and the periphery region and core regions. Subsequently, another photo resist film 14 is coated on the entire surface and then patterned by an exposure and development process so as to remain over the source/drain regions 9 between the gate electrodes 5 over the cell region.
Referring to FIG. 1D, using the photo resist pattern 14 as a mask, the polysilicon layer 13 is anisotropically etched to form node contact pads 13a and 13b and a bitline contact pad 13c.
Referring to FIG. 1E, contact holes are formed to expose the source/drain regions 9 over the core and periphery regions. Subsequently, a conductive material such as aluminum, tungsten, or polysilicon is deposited on the entire surface and patterned to form node contact wire layers 15a and 15b on the node contact pads 13a and 13b, respectively, a bitline contact wire layer 15c on the bitline contact pad 13c, n.sup.+ -type wire layers 16a and 16b contacting with the source/drain regions 9 in the core and periphery regions, and p.sup.+ -type wire layers 17a and 17b contacting with the source and drain regions 9 in the second conductive type well 3 in the core and periphery regions, thereby completing the process steps of the conventional method for forming contact wires of a semiconductor device.
However, the conventional method has problems. Contact hole aspect ratios tend to be high, e.g., higher than 4, so the process tolerance must be made tighter. There is no pad for wire formation in core and periphery regions, which exaggerates miss-alignment.